Société : IC Resources Lieu : Alpes-Maritimes (Provence-Alpes-Côte-D'Azur)
Descriptif du poste
Société : IC Resources Catégorie : Stage Filiere : IT/Etudes, développement et intégration Lieu : Alpes-Maritimes (Provence-Alpes-Côte-D'Azur)
Mission
Exciting opportunity as an ASIC Engineer to join the world leader in network-on-chip interconnect technology integration and deployment for SoCs - South of France
As an ASIC Design Engineer, you would be involved in creating IPs for customer specifications, for a wide range of applications from AI to cars, mobile phones, IoT, cameras, and SSD controllers.
Key Responsibilities:
Write microarchitecture specification
RTL design for IPs
Help improve and refine processes, methodologies, and metrics
Supporting the Verification Team
Key Skills:
Experience in RTL design for complex ASIC projects
Knowledge of Verilog or SystemVerilog.
Knowledge of interconnect technology is a plus
Knowledge of Cache architecture is a plus.
Knowledge of AMBA protocols, ARM/MIPS processors, on-chip interfaces such as OCP & AXI
